module encrypter (
output reg out,
output reg l0,
input logic data,
input logic keyclk,
input logic reset
);

reg [15:0] LFSR;
//------------Internal Variables--------
wire        linear_feedback;
//-------------Code Starts Here-------
assign linear_feedback =  (LFSR[5] ^ LFSR[3] ^ LFSR[2] ^ LFSR[0]);

assign l0 = LFSR[0];

//initial LFSR <= 10;

always_ff @(posedge keyclk) //, negedge reset
begin
	if (LFSR == 0 || !reset)
	begin
		LFSR <= 10;
	end
	else
	begin
		LFSR <= {linear_feedback,
					  LFSR[15], LFSR[14], LFSR[13], LFSR[12],
					  LFSR[11], LFSR[10], LFSR[ 9], LFSR[ 8],
					  LFSR[ 7], LFSR[ 6], LFSR[ 5], LFSR[ 4],
					  LFSR[ 3], LFSR[ 2], LFSR[ 1]};
	end
	out <= (~data) ^ LFSR[0];
end
	
endmodule